The present invention relates to the fabrication of memory cell arrays and, more particularly, to the formation of a specialized bit line contact in the structure of a DRAM array.
Conventional memory device arrays include word lines running generally in parallel along one direction and bit line pairs running generally in parallel along a perpendicular direction. The memory cell includes a charge storage structure connected by a transistor to one of the bit line pairs. Each transistor is activated by a word line. A row of memory cells is selected upon activation of a word line. The state of each memory cell in the row is transferred to a bit line for sensing by sense amplifiers, each of which is connected to a pair of bit lines. The memory cell transfer transistors are formed in the substrate in a plurality of continuous active areas running generally in parallel to each other. To form a transistor in an active area, impurity doped regions are formed in the substrate along the length of each active area 24 to create the source and drain of the transistor. A word line forms the gate of the transistor. The transistor formed in the active area provides the pass gate that is controllable to electrically connect the charge storage structure to a bit line. Thus, for example, activation of a word line will cause stored charges to be transferred by corresponding transistors to bit lines. The bit lines are electrically connected to a node of the transistor by bit line contacts.
Conventional bit line contacts are formed through a multi-step deposition and etch back process that increases the complexity of the overall array fabrication process. The process is further complicated because the upper surface of the bit line contact, i.e., the surface that serves as the conductive interface with the bit line, defines a V-shaped profile. Accordingly, there is a need for a memory array fabrication scheme that presents a simplified bit line contact fabrication process.